Frequently Asked Questions - Noise and Power Reduction

Power

Q: What is the importance of integrated-circuit power reduction? 

A:  High-power density is a serious problem in nanoelectronics design.  According to

the International Technology Roadmap for Semiconductors (ITRS), “power consumption is now one of the major constraints in chip design and the ITRS has identified it as one of the top three overall challenges for the last 5 years.”  Circuit heat generation is the main limiting factor for scaling of circuit speed and clocked-circuit density.  For a given CMOS technology, device speed is reduced at high temperature and clocked-circuit density increases the heat flux. Therefore, high-performance complex VLSI systems are bounded by power density since either speed or clocked-circuit density can be increased on a chip, but generally not both..    

Battery-powered applications can enjoy additional power reduction benefits.  Products employing reduced power techniques can dramatically extend battery life to provide competitive product advantage. 

Reduced power in all applications helps reduce energy consumption affording lower energy costs and helps reduce environmental entropy impacts. 

Q: How can InnovaClockControl^TM help reduce power consumption in integrated circuits?  

A:  Clocked-circuit power is a significant and often dominant power consumer in modern integrated circuits.  InnovaClockControl^TM is designed to reduce power in the active circuitry – whereas contemporary power reduction techniques work by shutting down inactive circuitry (e.g. clock gating and power gating).  InnovaClockControl^TM technology offers several power-reducing benefits. 

First, by judiciously scheduling tasks in a synchronous system, transient current (di/dt) and RMS current (causing power-bus heating) can be reduced.  RMS current reduction can reduce power-bus resistive losses 50%. 

Second, reduced peak current will minimize the power-grid dynamic voltage drop – thereby enabling lower chip operating voltage.  Conceptual simulations of reduced drop and reduced chip operating voltage indicated a 19% power reduction by this means alone.

Power Bus Integrity (Noise)

Q: What is power-bus integrity? 

A: Power-bus integrity is the ability of the integrated circuit, via its power-distribution network, to deliver constant voltage at any necessary current to the operating circuits.  The power distribution network is comprised of power (or multiple power) and ground (or multiple ground) busses, typically comprising a multi-layer metal grid across the integrated circuit.  The power grid is challenged to deliver constant (or clean) voltage by the VLSI or SoC high average current causing large ohmic IR voltage drops, and fast current transients that cause large inductive Ldi/dt voltage drops. 

Q: Why is power-bus integrity important? 

A: Power-bus integrity is important for a number of reasons. First, CMOS transistors used in industry operate slower with reduced voltage.  During VLSI or SoC operation, high average current and fast current transients cause power-bus “compression” – power-bus VDD drops while ground-bus voltage rises, reducing the voltage across the logic-gate CMOS transistors.  Power-bus compression can therefore cause timing and logic errors. Performance and function of the CMOS circuit can be severely compromised. 

Second, power-bus integrity ensures that noise margins of CMOS logic are sufficient across the integrated circuit.  High average current and fast current transients in the ground grid cause differences in ground potential, reducing noise margin and potentially causing performance failures in these CMOS circuits. 

Third, power-bus noise from digital logic can contaminate precision analog circuit functions such as communications blocks, PLLs, ADCs and DACs. 

Forth, power-bus noise can radiate from the chip as an Electromagnetic Interference (EMI), causing interference to adjacent circuits and/or jeopardizing regulatory emissions standards. 

Q: What technological trends are impacting the power integrity? 

A: Both average current and transient current are increasing at alarming rates.  The average current consumption in modern processors exceed 150 A, and future processors will have increased current requirements with continued process scaling.  At presents rates, processors will consume over 600 A by 2015!  Additionally, transient current in modern processors is about one tera-amp per second, the rate of increase in transient current is expected to at least double the rate of average current increase due to increasing clock frequency, as calculated by the International Technology Roadmap for Semiconductors (ITRS).  By 215 the expectation is 100 tera-amps per second!  Very little power bus parasitic inductance will incur enormous transient voltage drop in both power and ground busses. 

Q: What peak-current reduction is achievable and why is this important? 

A: 45 nm technology-mapped ISCAS’89 models have shown 38% to 45% peak current reduction.  Peak current reduction directly reduces the peak power-bus drop due to the power-bus (parasitic) resistance.  Peak current (I_PK) draw by CMOS circuits incurs voltage drop in both power and ground power busses due to I_PK*R_BUSS, where R_BUSS is bus resistance. 

Q: What rms current reduction is achievable and why is this important? 

A: Conceptual simulations have shown a readily obtainable 31% rms current reduction.  This rms current reduction reduces power bus heating and power-bus power loss by 50%. 

Q: What transient current reduction is achievable and why is this important? 

A: Conceptual simulations have shown a readily obtainable 75% transient current, di/dt, reduction.  High transient current is very problematic in power busses because power-bus parasitic inductance multiplied by the change in current (transient current, di/dt) begets power-bus voltage drop that starves CMOS logic circuits from their needed operating voltage.   The end results are numerous, including timing and logic errors.

Technology Description

Q: Briefly, what is InnovaClockControl^TM?

A: InnovaClockControl^TM is an RTL-level method that schedules circuit activities at optimal intervals within the unaltered clock period. When switching activities are redistributed more evenly across the clock period, IC supply-current consumption is also spread across a wider range of time within the clock period. This has the beneficial effect of reducing peak-current draw in addition to reducing rms power draw without having to change the operating frequency and without utilizing additional power supply voltages (as in dual or multi V_T approaches). In fact, InnovaClockControl^TM is complementary and can be utilized in conjunction with most power-reduction methods such as clock gating, multi- V_T, power switching/power shut-off; back-end process such as floor-plan and interconnect optimizations, and leakage-power reduction methods. 

Q: What is the Technology Readiness Level (TRL) of InnovaClockControl^TM?

A: InnovaClockControl^TM is presently at TRL3. The technology behind InnovaClockControl^TM has been proven in conceptual and benchmark simulations, such as ISCAS’89 models technology mapped to 45 nm.  Commercial tool flow is in development targeting the ARM series processor as a first demonstration by 2Q10.    We are seeking the appropriate industry partner for initial commercial integration beginning 3Q10. 

Q: Does InnovaClockControl^TM require any on-chip or external power supply or external components? 

A: No. 

Q: Does InnovaClockControl^TM require special fabrication process?

A: No. 

Q: Does InnovaClockControl^TM afford integrated-circuit chip or package cost reductions? 

A: Yes.  The peak current reduction can reduce the need for on-chip decaps, package decoupling capacitors, and on-board decoupling capacitors.  Reduced heat dissipation can reduce package type and cost significantly. 

Q: Can InnovaClockControl^TM be verified with existing timing and functional simulation tools? 

A: Yes.  InnovaClockControl^TM is consistent with existing RTL design constructs and integrates with existing tool-flows with minimal impact.

Performance

Q: Will the clock rate be adversely impacted using InnovaClockControl^TM ? 

A: The clock rate will not be decreased.  In fact, with improved power-grid integrity (reduced VDD drop and reduced ground bounce) CMOS transistors operate faster – the clock rate could be increased slightly. 

Q: What are the complexity, area and power overhead impacts of incorporating InnovaClockControl^TM ? 

A: InnovaClockControl^TM hardware is relatively low complexity.  Circuit complexity is minimized by the use of special algorithms in the design optimization tool-flow. 

Power overhead is dependent upon the integrated-circuit design. As an example, InnovaClockControl^TM circuit was analyzed for power consumption on ISCAS’85 circuit c432 -- the power overhead is only 3.2%. 

Area analysis of ten ISCAS’85 benchmark circuits technology-mapped to 45 nm, yielded a minimum area overhead 0.33 %, average area overhead 1.22 %, and maximum area overhead 2.73 %.