Frequently Asked Questions - Power Reduction and power integrity

InnovaClockControlTM provides a newly patented solution to reduce integrated circuit power consumption and to improve power integrity to help meet performance targets.

Power Reduction

Q: What is the importance of integrated-circuit power reduction? 

A: High-power density is a serious problem in nanoelectronics design. According to the International Technology Roadmap for Semiconductors (ITRS), “power consumption is now one of the major constraints in chip design and the ITRS has identified it as one of the top three overall challenges for the last 5 years”. Circuit heat generation is the primary limiting factor for scaling of circuit speed and clocked-circuit density. For a given CMOS technology node, device speed is reduced at high temperature and clocked-circuit density increases the heat flux. Therefore, high-performance VLSI systems are bounded by power density since either speed or clocked-circuit density can be increased on a chip, but not both.

Battery-powered applications can enjoy additional power reduction benefits. Products employing reduced power techniques can dramatically extend battery life to provide competitive product advantage.

Reduced power in all applications helps reduce energy consumption affording lower energy costs and helps reduce environmental impacts.

Q: How can InnovaClockControl help reduce power consumption in integrated circuits?

A:  Clocked-circuit power is a significant and often dominant power consumer in modern integrated circuits.  InnovaClockControl is designed to reduce power in the active circuitry – whereas many contemporary power-reduction techniques work by shutting down inactive circuitry (e.g. clock gating and power gating). InnovaClockControl technology offers the following power-reducing benefits for the active circuits: 

First, by judiciously scheduling tasks in a synchronous system, transient current (di/dt) and RMS current (causing power-interconnect heating) can be reduced.  RMS current reduction can reduce power-interconnect resistive losses 50%. 

Second, reduced peak current will minimize the power-interconnect dynamic voltage drop – thereby enabling lower chip DC operating voltage.  Conceptual simulation of reduced drop and reduced chip DC operating voltage indicated a 19% power reduction by this means alone.

Power Integrity (Power Noise Mitigation)

Q: What is IC power integrity? 

A: Integrated Circuit (IC) power integrity refers to the Power Delivery Network (PDN) ability to deliver a prescribed and constant voltage, at any necessary current, to the operating circuits. The PDN is generally comprised of power and ground interconnects, often configured as a multi-layer metal grid across the IC. The PDN is challenged to deliver constant (or clean, noise free) voltage by the IC high average current causing large ohmic IR voltage drops, and fast current transients that cause large inductive Ldi/dt voltage drops in the PDN.

Q: Why is power integrity important? 

A: IC power integrity is imperative for a number of reasons.  First, CMOS transistors operate slower with reduced voltage.  During IC operation, high average current and fast current transients cause PDN voltage “compression” – IC supply voltage drops while ground voltage rises, reducing the voltage across the logic-gate CMOS transistors. This voltage “compression” can therefore cause CMOS-logic timing and logic errors. Hence, IC performance and function can be severely compromised.

Second, power integrity ensures that the noise margins of CMOS logic are sufficient for all logic circuits across the integrated circuit.  High average current and fast current transients in the ground interconnects cause differences in ground potential, reducing noise margin and potentially causing performance failures in these CMOS circuits. 

Third, PDN voltage variations, or noise resulting from high-speed digital logic can contaminate precision analog circuit functions such as communications blocks, PLLs, ADCs and DACs.

Fourth, PDN noise can radiate from the chip interconnects causing interference to adjacent circuits and/or fail product compliance with world-wide Electro-Magnetic Interference (EMI) regulations (for example, FCC and DoD in the United States, CSA in Canada, VCCI in Japan, CISPR in Europe).

Q: What technological trends are impacting IC power integrity?

A: Both average current and transient current trends are increasing in high-performance ICs at alarming rates.  The average-current consumption in modern processors exceed 100 A, and future processors will have increased current requirements with continued process scaling.  At present rates, processors will consume over 600 A by 2015!  Additionally, transient current in modern processors is about 20 tera-amps per second, the rate of increase in transient current is expected to at least double the rate of average current increase due to increasing clock frequency, as calculated by the International Technology Roadmap for Semiconductors (ITRS). By 2015 the expectation is 100 tera-amps per second!  Very little PDN parasitic inductance will incur enormous transient voltage compression and starve CMOS logic of power.

Q: What peak-current reduction is achievable and why is this important?

A: Simulations of 45-nm technology-mapped ISCAS’85 models have demonstrated up to 72% peak-current reduction with InnovaClockControl.  Peak-current reduction directly reduces the peak PDN voltage drop due to the PDN (parasitic) resistance.  Peak current (IPK) draw by CMOS circuits incurs voltage drop in both power and ground PDN due to IPK*RPDN, where RPDN is the PDN resistance. 

Q: What rms current reduction is achievable and why is this important? 

A: Conceptual simulation using InnovaClockControl has shown that 31% rms current reduction is readily attainable.  This rms current reduction reduces PDN heating and PDN power loss by 50%. 

Q: What transient current reduction is achievable with InnovaClockControl and why is this important? 

A: InnovaClockControl conceptual simulation has shown an easily obtainable 75% transient current, di/dt, reduction.  High transient current is very problematic in the PDN because interconnect parasitic inductance multiplied by the change in current (transient current, di/dt) causes dynamic interconnect voltage drop that starves CMOS logic circuits of their needed operating voltage.  The end results are numerous, including timing and logic errors.  Recall that transient current is expected to reach 100 tera-amps per second by 2015!

Technology Description

Q: Briefly, what is InnovaClockControl?

A: InnovaClockControl is a Register Transfer Level (RTL) method that schedules circuit activities at optimal intervals within the unaltered clock period. When switching activities are redistributed more evenly across the clock period, IC supply-current consumption is also spread across a wider range of time within the clock period. This has the beneficial effect of reducing peak-current draw in addition to reducing rms power without having to change the operating frequency and without utilizing additional power supply voltages (as in dual or multi VT approaches). In fact, InnovaClockControl is complementary and can be utilized in conjunction with most power-reduction methods such as clock gating, multi- VT, power switching/power shut-off; back-end process such as floor-plan and interconnect optimizations, and leakage-power reduction methods. InnovaClockControl is implemented in a patented method that minimizes clock power and can take advantage of the benefits afforded by new optimizing clock routers.

Q: What is the Technology Readiness Level (TRL) of InnovaClockControl?

A: InnovaClockControl is presently at TRL3. The technology behind InnovaClockControl has been proven in conceptual and benchmark simulations utilizing ISCAS’85 models and OpenCores (including LEON 32-bit multiplier and Intel 8051 core ALU), technology mapped to 45-nm. InnovaClockControl tool flow is presently developed for SPARC 32-bit workstation on Sun Solaris OS (SunOS) version 5.10.

Q: Does InnovaClockControl require any on-chip or external power supply or external components?

A: No. 

Q: Does InnovaClockControl require special fabrication process?

A: No. 

Q: What impact does InnovaClockControl have on integrated-circuit chip or package cost? 

A: InnovaClockControl may significantly reduce IC packaging cost.  Its peak current reduction capabilities minimize the need for on-chip decaps, package decoupling capacitors, and on-board decoupling capacitors.  Certain on-chip decaps can leak significant power-supply current, so reduction of these decaps can reduce static power consumption. Reduced heat dissipation can reduce package type and cost significantly. 

Q: Can InnovaClockControl be verified with existing timing and functional simulation tools?

A: Yes, InnovaClockControl is consistent with existing RTL design constructs and integrates to existing tool-flows with minimal impact.


Q: Will the clock rate be adversely impacted using InnovaClockControl?

A: The clock rate will not be decreased.  Simulations and timing verifications for every benchmark was performed at maximum operating speed.  As examples, the ISCAS-85 c6288 (16 X 16 multiplier, 45 mn) was simulated and verified at its maximum operating speed of 870 MHz.  Similarly, the OpenCores 8051 ALU (45 nm) was simulated and verified at its maximum operating speed of 2.30 GHz.  In fact, with improved power integrity (reduced PDN voltage compression) CMOS transistors operate faster – the clock rate could be increased slightly. 

Q: What are the complexity and area overhead impacts of incorporating InnovaClockControl?

A: InnovaClockControl hardware is relatively low complexity. Circuit complexity is minimized by the use of special algorithms in the design-optimization tool flow.  InnovaClockControl execution time is only 2 to 3 minutes for any of the ISCAS-85 benchmarks using a SUN Sparc workstation having a single 2.5-GHz processor with 4 GB memory. Execution time scales linearly with circuit complexity.

Analysis of all circuits that we have incorporated InnovaClockControl, comprising ISCAS’85 benchmark circuits and OpenCores circuits technology-mapped to 45-nm averaged only 1.6% area overhead (range, 3.7% maximum to 0.2% minimum area overhead).


This page may include predictions, estimates or other information that might be considered forward-looking. While these forward-looking statements represent our current judgment on what the future holds, they are subject to risks and uncertainties that could cause actual results to differ materially. You are cautioned not to place undue reliance on these forward-looking statements, which reflect our opinions only as of the date of this presentation. Please recognize that we are not obliged to revise or publicly release the results of any revision to these forward-looking statements in light of new information or future events.