EDA Tool Integration

The InnovaClockControlTM architecture integrates seamlessly with industry-standard IC design tool flows.

innovaclockcontrol design flow optimization

A technology-mapped structural-level netlist is provided as input to InnovaClockControl. Peak-power reduction is performed utilizing an input vector set (not explicitly shown), while clock loading is concurrently optimized by InnovaClockControl. The resulting output from InnovaClockControl is a re-synthesized netlist exhibiting reduced peak power while maintaining full logic functionality and timing. Additional output includes timing constraints for an Optimizing Clock Tree Synthesizer (OCTS).

innovaclockcontrol IC design flow
 

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