EDA Tool Integration

The InnovaClockControlTM architecture integrates seamlessly with industry-standard IC design tool flows.

innovaclockcontrol design flow optimization

A technology-mapped structural-level netlist is provided as input to InnovaClockControl. Peak-power reduction is performed utilizing an input vector set (not explicitly shown), while clock loading is concurrently optimized by InnovaClockControl. The resulting output from InnovaClockControl is a re-synthesized netlist exhibiting reduced peak power while maintaining full logic functionality and timing. Additional output includes timing constraints for an Optimizing Clock Tree Synthesizer (OCTS).

innovaclockcontrol IC design flow

This page may include predictions, estimates or other information that might be considered forward-looking. While these forward-looking statements represent our current judgment on what the future holds, they are subject to risks and uncertainties that could cause actual results to differ materially. You are cautioned not to place undue reliance on these forward-looking statements, which reflect our opinions only as of the date of this presentation. Please recognize that we are not obliged to revise or publicly release the results of any revision to these forward-looking statements in light of new information or future events.