Innovative Solution for Low-Power Low-Noise Integrated Circuits
InnovaClockControlTM offers newly patented solutions to reduce IC power consumption and to improve Power Delivery Network (PDN) integrity.
Today’s nanometer VLSI and SoC designs are challenged with physical power-density limits and product power-consumption requirements. Meeting these challenges can afford reduced packaging costs (due to reduced heat dissipation), increased long-term reliability, increased battery life in portable applications, and decreased power consumption in high-performance systems.
Additionally, nanometer CMOS circuit operation is impacted by PDN noise in the form of VDD drop and ground bounce. Increased on-chip decaps, package and board decoupling capacitors along with power-interconnect width increases and/or PDN re-design are potentially expensive approaches to help mitigate power noise. Finally, PDN noise can radiate problematic EMI.
InnovaClockControl offers patent-pending solutions to reduce IC power consumption and to improve power integrity. Our technology directly addresses two of the top five challenges identified by the International Technology Roadmap for Semiconductors (ITRS) -- power and electronic noise.
InnovaClockControl provides a clean approach to reduce power and noise as a front-end design solution. There is no additional external-supply voltage and no off-chip passive components required. It is fully compatible with existing libraries and tool flows.
- Dynamic Power: Clock Polarity Assignment with Clock Buffer Sizing, Gate Sizing, Power Gating, Clock Gating, Voltage Scaling, Frequency Scaling
- Static Power: sub-threshold leakage reduction via Vth scaling (MTCMOS, VTCMOS, DTCMOS), gate-oxide reduction (multiple oxide MOXCMOS, multiple dielectric MKCMOS)
InnovaClockControl also complements low-power operational-transform techniques:
- Operation reduction and operation substitution, scheduling and pre-computation algorithms
InnovaClockControl has three embodiments and three IP licensable products:
1. Low-power technology for ACTIVE logic, enabling full performance
- Useful in cost-sensitive applications
-- Reduce chip peak power and peak current demands
-- Potentially reducing chip area and leakage current (via decaps reduction)
-- Reducing package cost (lower Theta-JC requirement), reducing metal layers
2. Lower-noise for mixed-signal SoC
- Peak noise reduction
- Reduce ground-grid and power-grid noise and crosstalk
3. SoC noise de-correlator
- Timing pseudo-randomizer (bounded)