Innovative Solutions for Low-Power Low-Noise Integrated Circuits

InnovaClockControl^TM offers patent-pending solutions to reduce IC power consumption and to improve power-grid integrity.

Power

Today’s nanometer VLSI and SoC designs are challenged with physical power-density limits and product power-consumption requirements.  Meeting these challenges can afford reduced packaging costs (due to reduced heat dissipation), increased long-term reliability, increased battery life in portable applications, and decreased power consumption in high-performance systems.

Noise

Additionally, nanometer CMOS circuit operation is impacted by power-bus noise in the form of VDD drop and ground bounce. Increased on-chip decaps, package and board decoupling capacitors along with power-bus width increases and/or power-grid re-design are potentially expensive approaches to help mitigate power-bus noise. Finally, power-bus noise can radiate problematic EMI.

East-West Innovation's InnovaClockControl^TM technology offers patent-pending solutions to reduce IC power consumption and to improve power-grid integrity. Our technology directly addresses two of the top five challenges identified by the International Technology Roadmap for Semiconductors (ITRS) -- power and electronic noise.

InnovaClockControl^TM provides a clean approach to reduce power and noise as a front-end design solution.  It is fully compatible with existing libraries and tool flows.

InnovaClockControl^TM