Low-Power Integrated Circuit Design Solutions

Low power consumption is a key requirement in most VLSI and SoC designs. Common low-power design methods utilize clock gating, power switching, low-power (slow) gates or similar approaches. Additionally, SoC designs can have challenging target noise requirements.

InnovaClockControl reduces VLSI and SoC power consumption and power dissipation, while improving power delivery network (PDN) integrity. Unlike clock gating or power switching, InnovaClockControl achieves power reduction and noise reduction benefits on the active clocked chip circuitry.

InnovaClockControl architecture schedules logic operation to reduce VLSI and SoC peak current, to reduce PDN transient current di/dt, and to reduce rms current that can heat power grids. As power-interconnect IR drop and Ldi/dt are reduced, power-supply operating voltages can be reduced to reduce power consumption.

InnovaClockControl^TM High-Level Conceptual Diagram

InnovaClockControl is implemented at register transfer level (RTL) and tested through simulations using industry-standard tool flows on the ISCAS’85 benchmark circuits, OpenCore circuits and LEON processor multiplier circuit in 45-nm node CMOS. Experimental results indicate that peak power can be reduced:

• 72 % maximum
• 37 % average
• 9 % minimum

Experimental results also indicate that RMS (heating) Current can be reduced:

• 84 % maximum
• 63 % average
• 32 % minimum

The small area increase for InnovaClockControl depends on the design. In ISCAS’85 benchmark circuits technology mapped to 45 nm, the area increase is only 0.33% to 2.73% (1.22% average). InnovaClockControl significantly reduces the peak power without significantly increasing clock-power or area overhead.

RTL functional and timing verification are re-confirmed with standard tools.

InnovaClockControl is a revolutionary advance in clock architecture, affording SoC developers performance gains and cost advantages. It enables:

• Crosstalk reduction (due to reduced aggressor peak power and reduced di/dt)
• Reduced need for static-power and area-consuming MOS decaps
• Reduced peak-voltage drops in the PDN

1. Improves logic-function reliability

• Provides the MOS transistors the rail voltage necessary to meet timing budget
• Reduces logic-gate input dynamic threshold error by decreasing power-grid voltage fluctuations

2. Minimizes overlap conduction caused by power droop/ground bounce and timing push-out/edge-rate reduction

InnovaClockControl offers MEGA benefits including:

• Performance improvements (including increased SNR in mixed-signal SOC)
• Increased logic-operation speed
• Improved reliability (reduced chip operating temperature reduces aging rate and thermal-cycling stress
• Reduced power consumption (reduced operating cost, extended battery life)
• Reduced power dissipation (reduced heat-sink and thermal management requirements)
• Reduced chip size as a result of area reduction (potentially saving up to 20% in area from reduced use of MOS decaps)
• Package savings (fewer embedded decaps, smaller chip, reduced thermal management requirements)
• Seamless integration into existing technology and processes
• Scalability (process, frequency, core, I/O, 3D)