InnovaClockControl^TM - Low Power Integrated Circuit Design Solutions

Low power consumption is a key requirement in most VLSI and SoC designs. Common low-power design methods utilize clock gating, power switching, low-power (slow) gates or similar approaches. Additionally, SoC designs can have challenging target noise requirements.

InnovaClockControl^TM is a patent-pending solution to reduce your VLSI and SoC power consumption, reduce power dissipation, and improve power-grid integrity. Unlike clock gating or power switching, InnovaClockControlTM achieves power reduction and noise reduction benefits on the active clocked chip circuitry.

InnovaClockControl^TM architecture schedules logic operation to reduce VLSI and SoC peak current, to reduce power bus transient current di/dt, and to reduce rms current that can heat power grids. As power-bus IR drop and Ldi/dt are reduced, power-supply operating voltages can be reduced to reduce power consumption.

InnovaClockControl^TM High-Level Conceptual Diagram

InnovaClockControl^TM is implemented into a completed design at the RTL. The small area increase for InnovaClockControl^TM depends on the design. In ISCAS’85 benchmark circuits technology mapped to 45 nm, the area increase is only 0.33% to 2.73% (1.22% average). RTL functional and timing verification are re-confirmed with standard tools.